Dae-Hong Ko: Strain-engineering in advanced CMOS structures
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Dae-Hong Ko

 

Department of Materials Science and Engineering, Yonsei University

 

As the conventional method of scaling-down the device size of MOSFETs had faced limitations in performance improvement, alternative route of strain engineering has been gaining much attention.  SiGe stressors epitaxially grown in source and drain effectively introduced compressive stress in the Si channels not only for the planar type but also for the 3-D FinFETs in P-type MOSFETs.  In comparison, for N-type MOSFETs, Si[C][P] stressors have been developed for the generation of tensile stress in the MOSFET channels.  We investigated the strain distribution in nanoscaled MOSFET structures with SiGe and Si[C][P] in the source and drain regions for the planar-type MOSFETs and 3-D FinFET structures as well.  After the formation of stressors in the S/D regions with SiGe or Si[C][P] by selective epitaxial deposition, we characterized the induced strain using both nano beam electron diffraction (NBD) and reciprocal space mapping (RSM), and compared them with the simulation results.  The strain distributions depend on the various factors of stressor compositions, device dimensions and structures, and also post processes such as oxidation or silicidation.  In this report, we will discuss the several examples of the strain evolutions in the nano-scaled MOSFET structures including 3-D FinFETs.

Plenary lectures - YUCOMAT 2019

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